DRAM read and write circuit
US6631441B2 · kind B2 · utility
1Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2000 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Jul 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory circuit including a memory plane formed of an array of memory cells, as well as at least two cache registers enabling access to the memory plane and adapted to ensure the reading from and the writing into the memory. The circuit also includes several registers indicating the location of new words to be written, each of the indicative registers being coupled with one of the cache registers adapted to ensuring the writing into the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.