Technique for implementing high performance stable storage hierarchy in a computer network
US6631478B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1999 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Jun 18, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1435
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique is provided for implementing a high performance stable storage system which provides stable and fast storage services to applications built on top of one or more operating system (OS) kernels in a computer network. The stable storage hierarchy comprises at least two levels of stable storage. The first level of stable storage is provided by one or more byte-addressable stable memory regions (SMRs) which may reside within the main memory of the computer network. Each stable memory region (SMR) provides a data structure for storage of essential or key data related to one or more client processes. The SMR is configured to provide an access interface which supports atomic access to its data structure. The SMR is also configured to be resilient to application failures. Further the SMR is configured to support concurrent access of its data by multiple clients. Additionally, the SMR is configured to support incremental updating of data within its data structure using pointer-based data transfer technique. The second level of the high performance stable storage hierarchy includes any traditional file system based stable storage system which is configured to communicate with one …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.