Automatic generation of programmable logic device architectures
US6631510B1 · kind B1 · utility
18Cited by
10References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1999 |
| Grant date | Oct 7, 2003 |
| Priority date | — |
| Expiry date | Oct 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention consists of a new component called the Architecture Generation Engine added to the CAD system for implementing circuits into PLD architectures and for evaluating performances of different architectures. The Architecture Generation Engine converts a high-level, easily specified description of a PLD architecture into the highly detailed, complete PLD architecture database required by the internals of the CAD toolset in order to map a circuit netlist into the PLD. The Architecture Generation Engine also enables the performance evaluation of a wide variety of PLD architectures for given benchmark circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.