Clock buffer with DC offset suppression
US6633191B2 · kind B2 · utility
16Cited by
26References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 24, 2001 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | May 24, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018514
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes a differential amplifier providing a differential signal to a voltage follower. The output of the voltage follower is fed back through resistors to an additional differential amplifier to the respective inputs to the voltage follower. The feedback is negative at low frequencies and less negative or positive about the clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.