Method and apparatus for digitally removing a DC-offset smaller than one LSB
US6633618B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1999 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | Dec 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal path, such as receiver signal path of a mobile station, includes an analog to digital converter (ADC) for representing an input signal as n-bits, the n-bit representation including a DC offset component. The signal path also includes a summing node having a first input for inputting the n-bit output of the ADC and a second input for inputting a k-bit representation of a DC offset component compensation value, where k=n+m, where m is a number of bits that represent a value smaller than one least significant bit (LSB) of said n-bit representation. The summing node operates to subtract the value appearing at the second input from the value appearing at the first input, and outputs a k-bit DC offset compensated value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.