Apparatus and method for sharing overflow/underflow compare hardware in a floating-point multiply-accumulate (FMAC) or floating-point adder (FADD) unit
US6633895B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2000 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | Feb 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method provide for performing either an overflow or underflow comparison while minimizing overflow/underflow comparison circuitry. In particular, the apparatus and are implemented with overflow/underflow possible check circuitry that determines if a mathematical operation between a first exponent signal and a second exponent signal creates a potential overflow condition. The overflow/underflow possible check circuitry generates a signal indicating whether an overflow or underflow condition is a possibility. Exponent compare circuitry computes an actual overflow or underflow condition. The exponent compare circuitry computes an actual overflow condition if the signal, from the overflow/underflow possible check circuitry, indicates that overflow is possible, and computes an actual underflow condition if the signal, from the overflow/underflow possible check circuitry, does not indicate overflow is possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.