Device and method to minimize data latency and maximize data throughput using multiple data valid signals
US6633927B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1999 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | Dec 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device and method for servicing data requests from a processor or other input/output interface in a multi-processor environment by accessing a full or partial cache line of data. A system data chip is used to access the cache line of data using a bit pattern supplied by a system address chip. This access and transmission of data to the processor or the input/output interface is controlled by a control/status unit in the system data chip based on the value of control valid signals which include a first valid (DxV) signal and a second valid (CxV) signal. Also, data may be stored and retrieved in a first data format (linear chunk order) or a second data format (critical chunk order). When control by the control/status unit is based on the DxV signal value, a read of a data chunk may occur immediately after a write to temporary storage if the data is in the same chunk order and a merge or combination operation is not taking place. When control by the control/status unit is based on the CxV signal, the entire cache line of data must be written to temporary storage prior to the reading of any data. In this way read operation are optimized to minimize latency and maximize throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.