Fully connected cache coherent multiprocessing systems
US6633945B1 · kind B1 · utility
47Cited by
49References
10Claims
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Key dates
| Filing date | Jul 8, 1999 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | Jul 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17375
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Fully connected multiple FCU-based architectures reduce requirements for Tag SRAM size and memory read latencies. A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.