Multiprocessor computer system and method for maintaining cache coherence utilizing a multi-dimensional cache coherence directory structure
US6633958B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 1997 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | Aug 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0826
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache coherence system and method for use in a multiprocessor computer system having a plurality of processor nodes, a memory and an interconnect network connecting the plurality of processor nodes to the memory. Each processor node includes one or more processors. The memory includes a plurality of lines and a cache coherence directory structure having a plurality of directory structure entries. Each of the directory structure entries is associated with one of the plurality of lines and each directory structure entry includes processor pointer information, expressed as a set of bit vectors, indicating the processors that have cached copies of lines in memory. Processor pointer information may be a function of a processor number assigned to each processor; the processor number may be expressed as a function of a first set of bits and a second set of bits which are respectively mapped into first and second bit vectors of the n bit vectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.