Controlling access to multiple memory zones in an isolated execution environment

US6633963B1 · kind B1 · utility

Assignee

• Intel Corporation · US

Inventors

• Carl M. Ellison · Portland, US
• Roger Golliver · Beaverton, US
• Howard C. Herbert · Phoenix, US
• Derrick C. Lin · San Mateo, US
• Francis X. McKeen · Portland, US
• Gilbert Neiger · Hillsboro, US
• Ken Reneris · Wilbraham, US
• James A. Sutton · Portland, US
• Shreekant S. Thakkar · Portland, US
• Millind Mittal · Palo Alto, US

Key dates

• Filing date: Jul 18, 2000
• Grant date: Oct 14, 2003
• Expiry date: Oct 23, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/1441
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor having a normal execution mode and an isolated execution mode generates an access transaction. The access transaction is configured using a configuration storage that stores configuration settings. The configuration settings include a plurality of subsystem memory range settings defining memory zones. The access transaction also includes access information. A multi-memory zone access checking circuit, coupled to the configuration storage, checks the access transaction using at least one of the configuration settings and the access information. The multi-memory zone access checking circuit generates an access grant signal if the access transaction is valid.