Design verification by symbolic simulation using a native hardware description language
US6634012B2 · kind B2 · utility
12Cited by
2References
18Claims
0Family size
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Key dates
| Filing date | Sep 14, 1999 |
| Grant date | Oct 14, 2003 |
| Priority date | — |
| Expiry date | Sep 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for performing design verification is described. In one embodiment, a method for performing design verification includes specifying at least one object that represents at least one signal as a symbol in a design using a first command and instructing a symbolic simulator with the first command to treat the at least one object as a symbol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.