SRAM layout for relaxing mechanical stress in shallow trench isolation technology
US6635936B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2000 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Jul 14, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
An SRAM device has STI regions separated by mesas and doped regions including source/drain regions, active areas, wordline conductors and contacts in a semiconductor substrate is made with a source region has 90° transitions in critical locations. Form a dielectric layer above the active areas. Form the wordline conductors above the active areas transverse to the active areas. The source and drain regions of a pass gate transistor are on the opposite sides of a wordline conductor. Form the sidewalls along the <100> crystal plane. Form the contacts extending down through to the dielectric layer to the mesas. Substrate stress is reduced because the large active area region formed in the substrate assures that the contacts are formed on the <100> surfaces of the mesas are in contact with the mesas formed on the substrate and that the <110> surfaces of the silicon of the mesas are shielded from the contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.