High isolation, low power high speed multiplexer circuit
US6636077B1 · kind B1 · utility
6Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 1999 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Jun 11, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6264
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-isolation, low-power high-speed multiplexer circuit suitably includes a buffer stage and a current steering tree stage. By employing common select lines for both stages of the circuit, both the input buffer and the deselected channel provide cumulative isolation for the deselected channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.