Digital receive phase lock loop with cumulative phase error correction
US6636092B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2000 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Nov 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital PLL's stability and immunity to jitter are improved by deriving the correction to the state machine count from an average over several computations of the phase error. The PLL stability is improved by retaining all of the phase errors measured during a succession of plural phase measurement intervals. The plurality of phase errors thus obtained are averaged together, and the state machine internal count is corrected (updated) in accordance with this average, rather than according to an instantaneous phase error. As a result, the performance of the PLL is less susceptible to jitter-induced temporary excursions in the phase error, a significant advantage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.