Upscaled clock feeds memory to make parallel waves
US6636096B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Oct 3, 2001 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | May 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit has a clock input for receiving a primary clock signal, clock reconfiguring device fed by the clock input for generating one or more secondary reconfigured clock signals, and utility circuitry fed by the clock reconfiguring device for constituting application utility functions under synchronization by the secondary clock signals. In particular, the clock input a clock upscaling device for from the primary clock signal generating an intermediate clock signal with an upscaled frequency for thereby feeding the clock reconfiguring device. Furthermore, the clock reconfiguring device a has late-programmable and low power memory driven by the intermediate clock signal for generating the secondary reconfigured clock signals. These are wave-shape patterns read-out from a plurality of separately and sequentially drivable memory locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.