Multibit memory point memory
US6636434B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 14, 2002 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Jun 14, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5617
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ROM including a set of memory points arranged in rows and columns, in which each memory point, formed of a single controllable switch, memorizes an N-bit information, with N>=2. Each column includes 2N conductive lines; each of the two main terminals of each memory point is connected to one of said conductive lines, each information value being associated with a specific assembly of 2N connections from among the set of 22N possible connections; and each of N read means is provided to apply a precharge voltage to a chosen group of 2N−1 first lines, connect the 2N−1 other lines to a reference voltage, select a memory point, read the voltages from the first lines, combine the obtained results to provide an indication of the value of one of the bits of the information contained in the selected memory point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.