Semiconductor memory device having improved data transfer rate without providing a register for holding write data
US6636444B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2002 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Jan 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device has a read data line, a write data line, a data holding circuit, and a data writing circuit. The data holding circuit holds data on the write data line, and the data writing circuit writes the data held on the write data line into a memory cell. Further, a semiconductor memory device has a read data line, a write data line, and an address information holding circuit. The address information holding circuit holds address information that is input in relation to write data, and when an access occurs to the address held in the address information holding circuit, data held on the write data line is written into a memory cell corresponding to the address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.