Semiconductor memory device that operates in synchronization with a clock signal
US6636455B2 · kind B2 · utility
2Cited by
6References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 2002 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | May 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This DDR SDRAM, in the normal operation mode, performs a writing operation having a writing latency and, in the testing mode, performs a writing operation without having a writing latency by receiving a data strobe signal and a data signal one clock cycle before a writing command. Therefore, the testing time is short even if the test is carried out at a low frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.