Bus interface circuit preparation apparatus and recording medium
US6636925B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2000 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Dec 28, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0646
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for automatically preparing a bus interface preparation apparatus is provided which is capable of preventing duplication of addresses of registers and memories. When data of a hardware description 10 are input into the extracting portion 101, the extracting portion 101 extracts from the data whether the memory element is a memory device or an FF. The extracting portion 101 reads the top address and the address size of the memory element when the memory is the memory element and reads address when the memory is an FF, and the thus read data are output to the address competition detecting portion 103. The address competition detecting portion 103 detects competition of the addresses by determining whether the address information stored in the bit data memory portion 102 includes 1. The output portion 104 converts the data concerning address of the memory into a description language of the hardware of the bus interface circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.