System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing
US6636949B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2002 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | May 3, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99952
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a chip multiprocessor system, the coherence protocol is split into two cooperating protocols implemented by different hardware modules. One protocol is responsible for cache coherence management within the chip, and is implemented by a second-level cache controller. The other protocol is responsible for cache coherence management across chip multiprocessor nodes, and is implemented by separate cache coherence protocol engines. The cache controller and the protocol engine within each node communicate and synchronize memory transactions involving multiple nodes to maintain cache coherence within and across the nodes. The present invention addresses race conditions that arise during this communication and synchronization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.