Crosstalk mitigation method and system
US6637014B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 16, 2001 |
| Grant date | Oct 21, 2003 |
| Priority date | — |
| Expiry date | Dec 8, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system of crosstalk mitigation in integrated circuits employs delay change curves (DCCs) and uses targeted transistor sizing and/or buffer insertion. Based on a timing graph, a longest path capable of being shortened may be shortened by victim strengthening or aggressor weakening when a setup requirement time violation occurs and the path is capable of being shortened. The process is repeated based on an updated timing graph until the longest path is not capable of being further shortened, or there is no setup requirement time violation. Additionally, the path may be lengthened where a hold requirement time violation has occurred and the path is capable of being lengthened, by victim strengthening or aggressor weakening, until the path cannot be further lengthened or there is no hold requirement time violation. Victim strengthening is performed by altering the critical path, and aggressor weakening is performed by altering the non-critical path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.