Hermetic chip scale packaging means and method including self test
US6638784B2 · kind B2 · utility
18Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1999 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Jun 24, 2019 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81B7/0077
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An integrated circuit chip and method of manufacturing the same which includes the use of a wafer cap having depressions therein for aligning with micro-electro-mechanical systems included in said integrated circuit when said cap is placed over a wafer containing numerous integrated circuits, the wafer is then cut, after the wafer cap is bound to the wafer. The wafer cap may also include a piezo-resistive element thereon for measuring pressure around the hermetically sealed MEMS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.