Semiconductor device with substrate-triggered ESD protection

US6639283B1 · kind B1 · utility

Assignee

• Faraday Technology Corp. · TW

Inventors

• Kei-Kang Hung · Changhua City, TW
• Ming-Dou Ker · Hsinchu, TW

Key dates

• Filing date: Apr 4, 2002
• Grant date: Oct 28, 2003
• Expiry date: Apr 4, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

A semiconductor device with substrate-triggered ESD protection technique includes a guard ring, a first MOS transistor array, a second MOS transistor array and a substrate-triggered portion. The first MOS transistor array, the second MOS transistor array and the substrate-triggered portion are formed in a region surrounded by the guard ring, and the substrate-triggered portion is located between the first MOS transistor array and the second MOS transistor array. Therefore, when the ESD event occurs, the substrate-triggered portion can be used for biasing a base of at least one parasitic BJT in the first MOS transistor array and a base of at least one parasitic BJT in the second MOS transistor array to achieve uniform turn-on among the multiple fingers of MOS transistor array. By using this layout design, the MOS transistor array can have a high ESD robustness.