Single layer surface mount package
US6639305B2 · kind B2 · utility
6Cited by
16References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2002 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Feb 1, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A single layer surface mount package suitable for use with a high frequency microelectronic device includes a lead frame partially embedded in a dielectric material and a lid. The dielectric material is integrally formed or molded into the cavities between the leads and die attach area of the lead frame such that at least the die attach area remains exposed on the top and the bottom surface of the dielectric material. A sufficient length of each lead remains exposed beyond the perimeter of the dielectric material for surface mounting to a circuit of a next level assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.