High linearity, high gain mixer circuit
US6639446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2002 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Jul 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D7/125
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A mixer circuit includes a first signal input terminal connected to the gate of a first MOSFET, and a second signal input terminal connected to the gate of a second MOSFET. The mixer circuit is configured such that a relationship (VG1−VGS2)<(VGS2−VT1) is established, where VG1 is a bias voltage applied to the gate of the first MOS transistor, VGS2 is a bias voltage applied to the gate of the second MOS transistor, and VT1 is a threshold voltage of the first MOS transistor, the bias voltages VG1 and VGS2 being each defined with respect to the source bias voltage of the second MOS transistor. This can implement high linearity mixer circuit even when operated at a low power supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.