Low standby power using shadow storage
US6639827B2 · kind B2 · utility
46Cited by
5References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2002 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Mar 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having CMOS transistors processed with different gate-oxide thicknesses. The transistors having the thinner gate-oxide may be used to generate data values that may be stored by the transistors having the thicker gate-oxides. The thicker gate-oxides may reduce gate leakage currents during a system standby mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.