Defect avoidance in an integrated circuit
US6639853B2 · kind B2 · utility
1Cited by
8References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 3, 2001 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Oct 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/90
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of using an integrated circuit with at least one defect, said method comprising the steps of determining the location of one or more defects in said integrated circuit; selecting a program to be stored on said integrated circuit, said program being selected on the basis of the location of said one or more defects; and loading said program onto said integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.