Integrated services hub self speed detection
US6640195B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2000 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Oct 17, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method of automatically detecting and storing the CPU clock frequency in a telecommunications hub. The hub includes a known reference clock for a digital signal processor. A first counter counts the reference clock cycles during the same time period in which a second counter counts the processor clock cycles. The number of processor clock cycles counted is divided by the number of reference clock cycles counted and the result is multiplied by the frequency of the reference clock. The calculated processor clock frequency is compared to a table of available CPU clock speeds and the closest available clock speed is selected. The selected available clock speed is then stored as a variable in RAM for use by all software which uses the processor clock as a base for generating absolute timing signals, such as a one second clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.