Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requests
US6640287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2002 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | May 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An invalid-to-dirty request permits a transition from an invalid memory state to a dirty state without requiring an up-to-date copy of the memory. The present invention is a system for supporting invalid-to-dirty memory transactions in an aggressive cache coherence protocol that minimizes directory entry locking. The nodes of a multiprocessor system each include a protocol engine that is configured to implement a distinct invalidation request that corresponds to an invalid-to-dirty memory transaction. If node O receives this distinct invalidation request while waiting for a response to an outstanding request for exclusive ownership, the protocol engine of node O is configured to treat the distinct invalidation request as applying to the memory line of information that is the subject of the outstanding request for exclusive ownership. Furthermore, if the node O receives a normal invalidation request, while it has an outstanding exclusive request, the invalidation request applies to a previous copy of the memory line of information held by the node N and therefore the protocol engine of node O is configured to ignore the normal invalidation request in this circumstance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.