Link pipe system for storage and retrieval of sequences of branch addresses
US6640297B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2000 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Mar 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The speed of processing of a sequence of indirect branch instructions in a pipelined processor is increased by overlapping the latencies in the sequence of indirect branch instructions. The architecture of a digital processor is modified to include a link pipe system that allows the sequence of branch addresses required by the indirect branches to be written to a single location within the processor, and to be read from a single location in the processor. The link pipe system contains a plurality of registers (3, 5 & 7) for storage of respective branch target addresses. Each WRITE of a branch address is automatically directed (9) to individual registers within the link pipe system for storing the respective branch addresses; and each READ of a branch address is automatically directed (11) to the register containing the earliest WRITE of an address that was not previously read by the processor, whereby branch target addresses are retrieved on a “first in, first out” basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.