Computer system providing low skew clock signals to a synchronous memory unit
US6640309B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2001 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Oct 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system is described including a processor for executing instructions, a memory module for storing instructions and data, and a memory controller coupled between the processor and the memory module. The memory controller provides a differential clock signal and memory access signals which are routed to the memory module. The memory module includes multiple memory devices coupled to a clock buffer. The clock buffer produces a new single-ended “regenerated” clock signal from the differential clock signal. The clock buffer includes an input buffer circuit and a phase-locked loop (PLL). The input buffer circuit receives the differential clock signal from the memory controller and produces a single-ended reference clock signal from the differential clock signal. The PLL produces the regenerated clock signal substantially at the same frequency of, and in synchronization with, the single-ended reference clock signal produced by the input buffer circuit. Each of the multiple memory devices is coupled to receive the regenerated clock signal, and the operations of the multiple memory devices are synchronized to the regenerated clock signal. The multiple memory devices w…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.