Microprocessor with high-reliability operating mode
US6640313B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1999 |
| Grant date | Oct 28, 2003 |
| Priority date | — |
| Expiry date | Dec 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/845
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a processor capable of operating in high reliability and high performance modes in response to mode switch events. Execution resources of the processor are organized into multiple execution clusters. An issue unit provides different instructions to the execution clusters in high performance mode. The issue unit provides the same instructions to the execution clusters in high reliability mode and results generated by the different execution clusters are compared to detect soft errors. The processor may be switched between the high reliability and high performance mode under software control or in response to the detection of certain conditions, such as the execution of certain types of process threads. These include process threads from the operating system kernel, process threads comprising uncacheable instructions, and machine check process threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.