Process for manufacturing a semiconductor wafer with passivation layer mask for etching with mechanical removal

US6642126B2 · kind B2 · utility

Assignee

• Micronas GmbH · DE

Inventor

• Gunter Igel · Teningen, DE

Key dates

• Filing date: Dec 21, 2000
• Grant date: Nov 4, 2003
• Expiry date: Dec 21, 2020

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/928
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A process for manufacturing a semiconductor arrangement (3), whereby in particular a wafer (1) with a large number of semiconductor arrangements forming chips (7) is manufactured, and the wafer is divided afterward, and in this way the semiconductor arrangements are separated. At least one region of a wafer side is covered by a passivation layer (9) during the etching of the remaining wafer area. After etching, the passivation layer (9) is removed. At least in an outer edge region of the wafer, if need be additionally in the shape of the wafer front side, outside the active chip surface and especially in the regions bounding the respective chip systems, adhesion zones (8) for the passivation layer (9) are created which enter into a sealing, and in particular a chemical combination with the material used for the passivation layer. Outside the adhesion zones, a diminished ability to adhere is present, so that the passivation layer (9), for example following the reverse side etching in the area lying outside the adhesion zones (8), can be removed from the wafer surface mechanically by one of a liquid stream, a gas stream, and by being acted upon by ultrasound.