Method for high temperature oxidations to prevent oxide edge peeling
US6642128B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2002 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Jul 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for preventing oxide layer peeling in a high temperature annealing process including providing a plurality of spaced apart stacked semiconductor wafers for carrying out a high temperature annealing process including ambient nitrogen gas the plurality of spaced apart stacked semiconductor wafers stacked such that a process surface including an oxide layer of at least one semiconductor wafer is adjacent to a backside surface of another semiconductor wafer said backside surface having a layer of silicon nitride formed thereon prior to carrying out the high temperature annealing process; and, carrying out the high temperature annealing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.