Long setup flip-flop for improved synchronization capabilities
US6642763B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 2001 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Dec 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device and method for improving the synchronization and metastability resolving capabilities of a flip flop. At least one master latch resolves a metastable condition of a received data signal thereby generating a stable data signal which is received and then displayed by a slave latch. Latches with superior metastability time resolution are configured in a master-slave relationship along with a novel clocking scheme whereby the clock signal supplied to the master latch is inverted as compared to that which is supplied to slave latch. As a result, the input data is latched on a falling edge of a clock signal and subsequently displayed on the rising edge of the clock signal providing at one half cycle for the input data to settle before passing out the data thereby allowing metastabilities to resolve during that period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.