Transmission-gate based flip-flop
US6642765B2 · kind B2 · utility
14Cited by
4References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2001 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Dec 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Flip-flop circuitry having an input configured to receive an input signal and an output configured to deliver an output signal corresponding to the input signal; a clock terminal configured to provide timing signals for reception of the input signal at the input and transmission of the output signal at the output; two on-path inverters connected serially between the input and output, and configured not to respond to the timing signals; and two feedback inverters respectively connected in parallel with the two on-path inverters, the first and second feedback inverters being configured to respond to the timing signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.