DC offset cancellation
US6642767B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 2002 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Sep 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0047
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
DC offset canceling is disclosed. A DC level fixing signal generator receives feedback input of two output signals from a mixer and generates a level fixing control signal to fix the DC level of the two output signals according to the input values. A DC offset canceling signal generator receives feedback input of two output signals from the mixer and generates offset canceling control signals to cancel the relative difference between the DC levels of the two output signals according to the input values. A DC level fixing and offset canceling circuit fixes the DC level of each of the two output signals from the mixer and cancels the relative difference between the DC levels of the two output signals according to the level fixing control signal and the offset canceling control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.