Apparatus and method for the correction of DC offset in data bus structures at the receiver
US6642868B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2002 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Jan 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
DC offset introduced into a differential signal is compensated for by DC offset correction circuitry. The DC offset correction circuitry receives a known training pattern of alternating logic high and logic low levels (i.e., 10101010 etc.). In one embodiment, the received signal is integrated and the result compared to a predetermined reference level. The result of the comparison is used to adjust a DC offset correction value that is added to the received signal. This process is iteratively performed until successive results of the comparison indicate that the DC offset has been compensated for in another embodiment, the duty-cycle of the received signal is calculated. The result of the duty-cycle calculation is used to iteratively adjust the DC offset correction value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.