Multi-processor graphics accelerator
US6642928B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2002 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | May 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/393
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that are transverse to the horizontal scan of the display. To that end, the first rasterizer has an input for receiving polygon data relating to the polygon. The first rasterizer determines a first set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the first set of pixels. Similar manner, the second rasterizer also includes an input for receiving polygon data relating to the polygon. The second rasterizer similarly determines a second set of pixels that are to be lit for display of the polygon, and also determines display characteristics of the second set of pixels. The first and second sets of pixels have no common pixels and are vertical stripes of pixels on the display device that are transverse to the direction of the horizontal scan.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.