Cubic memory array
US6643159B2 · kind B2 · utility
45Cited by
23References
66Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2002 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Apr 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cubic memory array is fabricated on a substrate having a planar surface. The cubic memory array includes a plurality of first select-lines organized in more than one plane parallel to the planar surface. A plurality of second select-lines is formed in pillars disposed orthogonal to the planer surface of the substrate. A plurality of memory cells are respectively coupled to the plurality of first and plurality of second select-lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.