Channel-erase nonvolatile semiconductor memory device
US6643183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2002 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Jul 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a channel-erase EEPROM, there is a parasitic capacitance between node N1 to which a substrate voltage is supplied and node N2 to which the voltage on a word line is supplied. A negative voltage is applied to the word line in erasing the data in a memory cell. A switch circuit SW1 is connected between node N1 and node N2. Between node N1 and the ground, a switch SW4 is connected. A switch SW5 is connected between node N2 and the ground. When the erase operation has been completed, the switch circuit SW1 is first turned on, short-circuiting node N1 and node N2. Thereafter, the switch circuits SW4, SW5 are turned on, grounding node N1 and node N2 separately.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.