Digital spread spectrum circuit
US6643317B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 25, 2000 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Feb 25, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2215/067
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A digital spread spectrum system provides a simple, digital device and method for reducing electromagnetic interference even where a clock signal to the device is rapidly turned on and off. A primary clock signal drives a signal selector. A signal delay is provided in the circuit to provide delayed clock pulse signals. The signal delay detunes the primary clock signal. By repeatedly switching the delay in and out of the clock signal path, a first signal is generated having a frequency at or about the clock signal, and, a second signal is generated which is displaced slightly from the first signal, but still at or about the clock frequency. By repeatedly switching the delay in and out of the primary clock signal path at a rate greater than the frequency of the clock signal, smaller portions of each primary clock pulse may be parsed for subsequent reaggregation to create a spread spectrum clock signal. As a result, a plurality of spread spectrum clock signals at varying frequencies may be created to spread the energy of the signal over a broader spectrum, thereby lowering the signal energy peak to minimize radiation of electromagnetic emissions at undesirable levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.