DC offset and bit timing system and method for use with a wireless transceiver
US6643336B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2000 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Apr 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W84/18
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An offset estimation and bit timing system and method configured to detect a DC offset in a received signal is disclosed herein. The inventive system includes a first circuit for receiving and correlating a transmitted signal and generating a trigger signal in response thereto. A second circuit accumulates the received signal and provides a second signal on receipt of the trigger signal. The second signal is then converted to an offset error signal. The error signal is converted to analog and used as a reference input for an A/D converter. As an alternative, the error signal may be used to adjust the signal output by an intermediate frequency downconversion stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.