Low cost memory management that resists power interruption
US6643731B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2000 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Nov 15, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0246
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for reliably managing a Flash ROM memory resource while preserving the integrity of the data held in the memory in spite of power outages that can occur during memory compressing operations. The memory management system uses three memory status registers to track the status to each page in the memory being managed. Two of the memory status registers give non-volatile memory and one is always determined to be the active memory status register. The third memory status register is located in RAM and used as a scratchpad. If the memory management routine determines the memory needs to be cleaned or compressed, the RAM memory status register is initialized and a swap segment is cleared. Valid pages are copied into the swap segment. After all of the valid pages from one application segment have been copied to the swap segment, the RAM memory status register is copied to a new valid non-volatile memory status register and the other non-volatile memory status register is erased at this time. The application segment is then cleaned. The swap segment is then copied to the cleaned application segment and any empty pages of the application segment are filled using additiona…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.