Random replacement generator for a cache circuit

US6643740B1 · kind B1 · utility

Assignee

• LSI Logic Corporation · US

Inventor

• Stefan Auracher · Baierbrunn, DE

Key dates

• Filing date: Jul 30, 2001
• Grant date: Nov 4, 2003
• Expiry date: Nov 23, 2021

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A cache may comprise a memory and control logic. The memory may be configured for storing data buffered by the cache. The control logic may be configured controlling accesses to the memory. The control logic may comprise a pseudo-noise generator and a trigger device. The pseudo-noise generator may be configured for generating a pseudo-random number representing, for a miss access requiring allocation, which of a plurality of possible addresses in the memory to use for the allocation. The trigger device may be configured for controlling a cycle of the pseudo-noise generator to output the pseudo-random number therefrom.