Method and apparatus for prefetching data into cache

US6643745B1 · kind B1 · utility

Assignee

• Intel Corporation · US

Inventors

• Salvador Palanca · Rancho Cordova, US
• Niranjan L. Cooray · Folsom, US
• Angad Narang · Rancho Cordova, US
• Vladimir Pentkovski · Folsom, US
• Steve Tsai · San Jose, US
• Subramaniam Maiyuran · Citrus, US
• Jagannath Keshava · Folsom, US
• Hsien-Hsin Sean Lee · Duluth, US
• Steve Spangler · Cameron Park, US
• Suresh Kuttuva · Folsom, US
• Praveen Mosur · Folsom, US

Key dates

• Filing date: Mar 31, 1998
• Grant date: Nov 4, 2003
• Expiry date: Jun 4, 2018

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/6028
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.