Cyclically sequential memory prefetch
US6643755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2001 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Dec 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/381
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory access architecture and technique employs multiple independent buffers that are configured to store items from memory sequentially. The memory is logically partitioned, and each independent buffer is associated with a corresponding memory partition. The partitioning is cyclically sequential, based on the total number of buffers, K, and the size of the buffers, N. The first N memory locations are allocated to the first partition; the next N memory locations to the second partition; and so on until the Kth partition. The next N memory locations, after the Kth partition, are allocated to the first partition; the next N locations are allocated to the second partition; and so on. When an item is accessed from memory, the buffer corresponding to the item's memory location is loaded from memory, and a prefetch of the next sequential partition commences to load the next buffer. During program execution, the ‘steady state’ of the buffer contents corresponds to a buffer containing the current instruction, one or more buffers containing instructions immediately following the current instruction, and one or more buffers containing instructions immediately preceding the cur…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.