Address generation unit and digital signal processor (DSP) including a digital addressing unit for performing selected addressing operations
US6643761B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2000 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | May 8, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30101
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address generation unit (AGU) and a digital signal processor (DSP) including such an AGU are disclosed. The AGU (3) has a register file (4) providing order (R), stage (S), and displacement (N) values to a digital addressing unit (DAU) (5) for performing one of eight addressing operations. The register file provides an input (X) to the DAU and receives an output (Y) from the DAU. Within the DAU (5), selection multiplexers (13, 14) select full adder outputs to provide Y, or bit-select from adders and the input (X) to provide Y. For a radix-4 operation, most significant bits (MSBs) are taken from the input (X), middle bits are taken from the output of a first adder (adder1), and the least significant bits (LSBs) are taken from the output of a second adder (adder2) if there is a carry out from the first adder. The AGU may also include bit reverse blocks connected at both the input and output of an adder. The DSP includes a program control unit for delivering a control signal to the AGU for selection of a required addressing operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.