Duty cycle correction circuit with frequency-dependent bias generator
US6643790B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2000 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Mar 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle correction circuit operates by alternately speeding and slowing successive transitions of an input clock signal. By altering the rising and falling edge rates of a clock signal asymmetrically, the duty cycle of the clock signal is adjusted without shifting the DC level of the clock signal. In one embodiment, the duty cycle correction circuit includes current sources in place of resistive loads to avoid shifting the DC level of output clock signals. Frequency-dependent current sources that generate increased bias currents at higher frequency are used to achieve duty cycle correction over a broad range of input frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.