Virtual tree-based netlist model and method of delay estimation for an integrated circuit design
US6643832B1 · kind B1 · utility
19Cited by
4References
15Claims
0Family size
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Key dates
| Filing date | Sep 26, 2001 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Nov 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pre-placement delay model for a logical function block of an integrated circuit design includes a fan-in count variable, a fan-out count variable and a delay variable. The fan-in count variable has a value indicative of a number of inputs to the logical function block. The fan-out count variable has a value indicative of the number of inputs of other logical function blocks that are driven by an output of the logical function block. The delay variable has a value that is a function of the binary logarithm of the fan-in count variable and the binary logarithm of the fan-out count variable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.